1. Field of the Invention
The present invention relates to a method of placing a plurality of delay units of a pulse delay circuit on a programmable logic device to delay a pulse signal in each of the delay units and on a line between two delay units in each pair.
2. Description of Related Art
A pulse delay circuit composed of a plurality of delay units has been utilized to delay a pulse signal in each of the delay units and to transmit the delayed signal to an external device. For example, in Published Japanese Patent First Publication No. H05-259907 and Published Japanese Patent First Publication No. H07-183800, this pulse delay circuit is used for a device such as a time measuring device, an analog-to-digital (A/D) converting device, a digital control oscillating device or the like.
To structure the device using the pulse delay circuit as integrated circuits, logic specifications of a programmable logic device (PLD) such as a field programmable gate array (FPGA) or the like are determined by programming. When the integrated circuits, of which the logic specifications are determined by programming, are laid out onto logic cells of the programmable logic device, the circuits are automatically placed on the device and are connected with one another.
However, in this automatic placement, the delay units are not always located in respective logic cells in the placement required for the proper operation of the pulse delay circuit. That is, because the pulse signal delayed in each delay unit by a unit delay time is further delayed on a transmission line between two delay units in each pair by a transmission delay time, a delay time between two delay units is equal to the sum of the unit delay time in one delay unit and the transmission delay time on a line between the delay units. To appropriately operate the pulse delay circuit, it is required that the delay time between two delay units in each pair is equal to delay times in other pairs of delay units. However, in the automatic placement, the transmission delay times in the pulse delay circuit become considerably different from one another, so that the delay times in pairs of delay units are differentiated from one another. In this case, digital data converted in the A/D converter having the pulse delay circuit, a period of time measured in the time measuring device having the pulse delay circuit or a frequency or phase controlled by the digital control oscillating device having the pulse delay circuit cannot be obtained with high precision.